// Version 2 of module for comparison test - with differences
module test_module (
    input wire clk,
    input wire rst_n,
    input wire [15:0] data_in,    // Changed from [7:0] to [15:0]
    output wire [7:0] data_out,
    output wire valid,
    output wire ready              // Added new port
);

parameter WIDTH = 16;              // Changed from 8 to 16
parameter DEPTH = 16;
parameter ENABLE = 1;              // Added new parameter

reg [7:0] internal_reg;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
        internal_reg <= 8'h0;
    else
        internal_reg <= data_in[7:0];
end

assign data_out = internal_reg;
assign valid = 1'b1;
assign ready = 1'b1;

endmodule
